1. Field of the Invention
The present invention relates to integrated circuit device elements and, in particular, to a dielectric-based anti-fuse cell and cell array, with a polysilicon contact plug and methods for their manufacture.
2. Description of the Related Art
Anti-fuse cells (also known as fusible links) are used as programmable interconnections in logic integrated circuit (IC) devices, such as Field Programmable Gate Arrays (FPGA), and memory IC devices.
A conventional oxide-nitride-oxide (ONO) dielectric-based anti-fuse cell is illustrated in FIG. 1. ONO dielectric-based anti-fuse cell 10 includes an N+ diffusion region 12 disposed on a semiconductor substrate 14. ONO dielectric layer 16 and doped polysilicon layer 18 are disposed above the N+ diffusion region 12. The doped polysilicon layer 18 and the N+ diffusion region 12 are separated by both the ONO dielectric layer 16 and an insulating layer 20, except in one region where the separation is accomplished solely by the ONO dielectric layer 16. Insulating layer 20 is also disposed on the upper surface of semiconductor substrate 14. As illustrated in FIG. 1, a portion of the N+ diffusion region 12 lies under a gap in the insulating layer 20, with the doped polysilicon layer 18 and its underlying ONO dielectric layer 16 filling the gap.
The ONO dielectric-based anti-fuse cell 10 of FIG. 1 is programmed to a conductive state by applying a voltage across the ONO dielectric layer 16 (i.e. the voltage is applied between the N+ diffusion region 12 and doped polysilicon layer 18 at the "gap" in the insulating layer 20) sufficient to rupture the ONO dielectric layer at the gap. Additional details of ONO-based anti-fuses, such as the anti-fuse cell illustrated in FIG. 1, are described in E. Hamdy et al., Dielectric Based Antifuse for Logic and Memory ICs, Technical Digest of the International Electron Devices Meeting, 786-787 (1988), which is hereby fully incorporated by reference.
A conventional dual-polysilicon and nitride-oxide (NO) dielectric-based anti-fuse cell 30 for use in FPGA applications is illustrated in FIG. 2. Anti-fuse cell 30 includes a doped polysilicon (poly 1) layer 32 that is separated from semiconductor substrate 34 by first insulating layer 36 (typically silicon dioxide). A second insulating layer 38 (typically silicon dioxide), with an opening therethrough, is disposed on the upper surface of poly 1 layer 32. A portion of the upper surface of the poly 1 layer 32 is exposed through the opening in the second insulating layer 38. A layer of NO dielectric 40 is disposed on the surface of second insulating layer 38, including on the sidewalls of the opening, and on the portion of the poly 1 layer that is exposed through the opening. A second doped polysilicon (poly 2) layer 42 overlies the layer of NO-dielectric 40 and further fills the opening in the second insulating layer 38.
The dual-polysilicon NO dielectric-based anti-fuse cell of FIG. 2 is programmed to a conductive state by applying a voltage across the layer of NO dielectric 40 (i.e. the voltage is applied between the poly 1 layer 32 and the poly 2 layer 42 at the opening in the second insulating layer 38) sufficient to rupture the NO dielectric at the opening. The use of an NO dielectric layer, rather than an ONO dielectric layer, reduces the voltage required to rupture the dielectric. See David K. Y. Liu et al., Scaled Dielectric Antifuse Structure for Field Programmable Gate Array Applications, IEEE Electron Device Letters, Vol. 12, No. 4, 151-153 (1991), which is hereby fully incorporated by reference, for a further description of dual-polysilicon NO dielectric-based anti-fuse elements.
Prior to being programmed, a dielectric-based anti-fuse cell is in a high resistance state due to the presence of a dielectric layer (either ONO or NO) separating the conductive layers (either a doped diffusion region in a semiconductor substrate or a doped polysilicon layer). After the anti-fuse cell is programmed (i.e. the dielectric is ruptured) by the application of a voltage ("anti-fuse programming voltage"), the anti-fuse cell assumes a relatively low resistance state and therefore becomes more conductive. In this "programmed" state, the resistance of the anti-fuse cell is dependent on the area and electrical properties of the contact between the conductive layers. The series resistance of a cell array is proportional to the length of the polysilicon lines connecting individual anti-fuse cells of the array.
Reducing (i.e. "scaling") the anti-fuse programming voltage of dielectric-based anti-fuses often requires thinning the dielectric layer. However, thinning the dielectric layer increases the anti-fuse capacitance, which causes an undesirable decrease in integrated circuit device speed (i.e. an increase in the time delay). The capacitance of the anti-fuse in the non-programmed state can be reduced by minimizing the contact area of the anti-fuse. However, when the contact area of a conventional anti-fuse is reduced, the resistance of the anti-fuse is increased, resulting in a reduction in device speed. In addition, there is a reduction in device speed due to the preexistence of undesirable anti-fuse cell array capacitance associated with the polysilicon lines employed to connect the individual cells of the array (e.g. capacitance between polysilicon lines and the substrate).
Still needed in the art is a dielectric-based anti-fuse cell, and a process for its manufacture, that allows for the area of the anti-fuse dielectric to be scaled along with the dielectric thickness, while still providing an anti-fuse cell with a low capacitance and a low resistance in the programmed state. It is desirable that the dielectric-based anti-fuse have a relatively small contact area, thereby decreasing anti-fuse capacitance while providing for an increased cell layout density with low series resistance. Also needed is a anti-fuse cell array with a low resistance in the programmed state, a low capacitance, a small cell area and high cell density. The process of manufacture for the cell and cell array should be simple and fully compatible with conventional Complimentary-Metal-Oxide-Semiconductor (CMOS) processing.